Digital Hardware Engineer

Job Locations US-Washington, D.C.
ID
2020-2220
Business Unit
CSE
Type
Full-Time
Clearance
Secret Required
Location : Location
US-Washington, D.C.

Overview

i3 has an exciting opportunity for a Digital Hardware Engineer to support the Naval Research Laboratory, Tactical Electronic Warfare Division. The TEWD's mission is to protect the warfighter from emerging threats by advancing electronic warfare (EW) through reverse engineering and RDT&E of current and future technologies.

Responsibilities

  • Design, implement, integrate, and test digital systems specifically regarding FPGA technology.
  • Develop Verilog, VHDL, HDL, and graphical designs for FPGAs.
  • Integrate manufacturer IP FPGA cores (processor, ADC, DAC, etc.) into customized firmware architectures.
  • Design and validate testbench routines for simulation of FPGA designs and sub-designs.
  • Integrate firmware with target hardware with systems components and software.

Qualifications

  • Security Clearance: Current Secret clearance with ability to possess TS/SCI.
  • Bachelor's degree in Electrical Engineering or Computer Engineering, and a minimum of five (5) years of experience required.
  • Thorough understanding and ability to reverse engineer primitive digital logic design.
  • Experience with communication protocols such as RS232, RS422, UART, SPI, I2C.
  • Ability to generate architectural design block diagrams from existing firmware designs.
  • Experience developing and testing Altera and Xilinx FPGAs.
  • Experience designing and developing software to integrate with FPGA and target platform systems.
  • Knowledge of Altera and Xilinx development environments.
  • Knowledge of Altera and Xilinx simulation and validation environment (i.e. Synplify, ModelSim, Verdi).
  • General knowledge of DSP coding and communication protocols.
  • US Citizenship

Preferred:

  • Knowledge of microprocessor architecture and high speed interfaces as applied to FPGA Core functions.
  • Ability to recognize DSP data paths, digital filters, FFTs, and error-correction codes.
  • Ability to design/recognize RF and/or 6DOF computational paths in both digital and analog design.

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